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H1A424M167
Image Signal Processor for Hyundai CMOS Image Sensor Data Sheet
Version 1.0
Electronics Industries Co., Ltd
Hyundai Electronics Industries Co., Ltd.
H1A424M167
REVISION HISTORY
Revision 0.45 0.9 Issue Date April 28, 1999 June 15, 1999 Comments Draft Added Suspend Pin(No.16) Added Flicker Free Banding noise filter Added Histogram Equalization function Added STATUS_FLAGS register Modified Gamma Correction function Modified AWB/AE function 0.95 August 10, 1999 Added CIF type CIS(HV7121X) support function Added X-flip function Modified Edge Enhancement filter JFIF color space conversion equation Modified BASE_ENB register Modified STATUS_FLAGS register Modified AWB/AE function 1.0 October 11, 1999 Added Functional Description/Register Description Added Soldering Description Formal Release
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TABLE OF CONTENTS
1. FEATURES ...................................................................................................................................... 5 2. PIN CONFIGURATION.................................................................................................................. 6 3. PIN DEFINITION............................................................................................................................ 7 4. SYSTEM DIAGRAM..................................................................................................................... 10 5. BLOCK DIAGRAM ...................................................................................................................... 10 6. VIDEO PROCESSING ENGINE BLOCK DIAGRAM ............................................................... 11 7. FUNCTIONAL DESCRIPTION.................................................................................................... 12 7.1. HOST INTERFACE ....................................................................................................................... 12 7.1.1. Serial Interface .................................................................................................................. 12 7.1.2. Host Parallel Interface ...................................................................................................... 14 7.1.3. Serial or Parallel Interface selection ................................................................................. 15 7.2. CLOCK(MCLK, PCLK, VCLK) TIMING DIAGRAM ..................................................................... 16 7.3. VIDEO OUTPUT INTERFACE......................................................................................................... 16 7.4. RELATIONS BETWEEN INPUT VIDEO TIMING AND OUTPUT VIDEO TIMING ........................................ 17 7.4.1. VGA................................................................................................................................... 18 7.4.2. CIF .................................................................................................................................... 18 7.4.3. SIF..................................................................................................................................... 19 7.4.4. QCIF ................................................................................................................................. 19 7.4.5. QSIF.................................................................................................................................. 20 8. REGISTER DESCRIPTION ......................................................................................................... 21 8.1. REGISTERS MNEMONIC TABLE.................................................................................................... 21 8.2. BASE REGISTER MAP................................................................................................................ 24 8.2.1. Normal Register[80h~83h]................................................................................................ 24 8.2.2. Color Matrix Coefficients Value[8Ah ~ 95h] ..................................................................... 26 8.3. AUTO REGISTER MAP ............................................................................................................... 29 8.3.1. Function Enable Register[A0h] ......................................................................................... 29 8.3.2. AWB/AE Windows Configuration Registers[A1h~A6h] ...................................................... 30 8.3.3. Normal Register[A7h~B8h] ............................................................................................... 31 8.4. OUT REGISTER MAP.................................................................................................................. 37 8.4.1. Normal Register[C0h~C2h]............................................................................................... 37
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8.4.2. Histogram Equalization Control Register[C3h~C4h] ........................................................ 38 8.4.3. Gamma Control Register[E0h~F1h].................................................................................. 39 9. ELECTRICAL CHARACTERISTICS ......................................................................................... 42 9.1. ABSOLUTE MAXIMUM RATINGS .................................................................................................. 42 9.2. DC CHARACTERISTICS ............................................................................................................... 42 9.3. AC CHARACTERISTICS ............................................................................................................... 43 9.3.1. Microcontroller Bus Interface timing (Write cycle) ............................................................ 43 9.3.2. Microcontroller Bus Interface timing (Read cycle)............................................................. 43 9.3.3. Serial Interface Control Timing ......................................................................................... 44 9.3.4. RESETB Timing................................................................................................................. 45 9.3.5. Video Output Timing.......................................................................................................... 45 10. PACKAGE SPEC......................................................................................................................... 46 11. SOLDERING................................................................................................................................ 47 11.1. SOLDER REFLOW EQUIPMENT .................................................................................................... 47 11.2. REFLOW PROFILES.................................................................................................................... 47 11.3. FLUX APPLICATION ................................................................................................................... 47 11.4. CLEANING ............................................................................................................................... 47 11.5. DRYING ................................................................................................................................... 47
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1. Features
n n n n n n n n n n n n n n n n n n n n n
Dedicated sensor control and signal processing chip for Hyundai CMOS Image Sensor CMOS 3.3V Device (0.5um CMOS TLM Process used) Serial-Bus interface or alternative 8-bit MCU parallel interface for register programming Serial-Bus interface for HYUNDAI CMOS Image Sensor Chip Control 8 bit Bayer format image input 3 x 3 Interpolation Color Correction matrix Gamma Correction Automatic Exposure Control Automatic White Balance Control Programmable AE/AWB windows Automatic Reset Level Control Edge Enhancement Support 2x2, 4x4 Sub-Sampling(CIF, QCIF) RGB to YCrCb Color Space Convert Histogram Equalization Logic 16bit YUV 4:2:2, YUV 4:2:0, 8bit YUV 4:2:2, YUV 4:2:0 video output format Flicker Free Banding noise filter X Flip Function for mirrored image Horizontal and Vertical Sync Information on Separate Pin 64 Pin LQFP Package(Standard JEDEC Package)
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2. Pin Configuration
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3. Pin Definition
Pin Number Pin Name Type Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SDA HSYNC VSYNC PD[0] PD[1] PD[2] VDD SCK VSS PD[3] PD[4] PD[5] PD[6] PD[7] NC SUSPEND ENB VDD PCLK VSS AD[0] AD[1] AD[2] AD[3] VDD MCLK VSS AD[4] AD[5] AD[6]
B I I I I I P O G I I I I I I O P O G B B B B P I G B B B
Serial Data for CMOS Image Sensor Control Horizontal SYNC Signal from CMOS Image Sensor Vertical SYNC Signal from CMOS Image Sensor Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip Power Pin, 3.3V Serial Clock for CMOS Image Sensor Control Ground Pin Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip Raw Pixel Data from Image Sensor Chip No Connection Suspend Mode Support Pin, Active high CMOS Image Sensor Enable Power Pin, 3.3V Pixel Clock for CMOS Sensor ( MCLK / 3 ) Ground Pin Address/Data Bus for MCU interface Address/Data Bus for MCU interface Address/Data Bus for MCU interface Address/Data Bus for MCU interface Power Pin, 3.3V Master Clock Input Ground Pin Address/Data Bus for MCU interface Address/Data Bus for MCU interface Address/Data Bus for MCU interface
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31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
AD[7] ALE IODONE UV[7] UV[6] UV[5] UV[4] VDD RESETB VSS UV[3] UV[2] UV[1] UV[0] VDD VCLK VSS Y[7] Y[6] Y[5] Y[4] VDD VSS Y[3] Y[2] Y[1] Y[0] HSISP VSISP VDD SCLK/IOR VSS SDATA/IOW
B I O O O O O P I G O O O O P O G O O O O P G O O O O O O P I G B
Address/Data Bus for MCU interface Address Latch Enable CIS/ISP Read/Write Done Video Data Output for CrCb Video Data Output for CrCb Video Data Output for CrCb Video Data Output for CrCb Power Pin, 3.3V ISP Reset, Active Low Ground Pin Video Data Output for CrCb Video Data Output for CrCb Video Data Output for CrCb Video Data Output for CrCb Power Pin, 3.3V Pixel Clock for Video Output Ground Pin Video Data Output for Y Video Data Output for Y Video Data Output for Y Video Data Output for Y Power Pin, 3.3V Ground Pin Video Data Output for Y Video Data Output for Y Video Data Output for Y Video Data Output for Y Horizontal SYNC Signal for Video Data Output Vertical SYNC Signal for Video Data Output Power Pin, 3.3V Serial Bus Clock for programming ISP, Can be used as IOR when MCU interface configuration Ground Pin Serial Bus Data for programming ISP, Can be used as IOW when MCU interface configuration
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64
CSB/MODE
I
ISP chip select when MCU interface configuration During reset time, this pin operates as interface mode
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4. System Diagram
HYUNDAI CMOS Image Sensor Image HSYNC VSYNC PD[7:0] PCLK ENB Serial Interface
H1A424M167 HYUNDAI ISP
HSISP VSISP Y[7:0] UV[7:0] VCLK Serial Interface or Parallel Interface
USB Controller
USB
MCLK
DRAM Video Buffer
5. Block Diagram
HSYNC VSYNC PD[7:0] PCLK ENB
Video Input Interface
Video Processing Engine
Video Ouput Interface
HSISP VSISP Y[7:0] UV[7:0] VCLK
SDA SCK
Serial Interface Master (to CIS)
MCU Interface ( Serial or Parallel )
Serial Interface or Parallel Interface
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6. Video Processing Engine Block Diagram
Bayer format RGB Stream
Interpolation to 24bit RGB
Color Correction
Gamma Correction
Color Space Conversion
Histogram Equalization
Edge Enhnacement
Format conversion
YCrCb Output Stream
YCrCb Y
Reset Level Offset Data
Auto White Balance Auto Exposure Anti Flicker Auto Reset Level
RGB Analog gain control Integration Time Setting
To CIS
Reset Level Setting
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7. Functional Description
7.1. Host Interface
Hyundai ISP chip supports two kinds of host interface, serial and 8bit parallel, to program ISP registers or to read ISP registers. And the host interface is also used to write or to read CMOS Image Sensor(CIS) registers through ISP. 7.1.1. Serial Interface The serial interface of Image Signal Processor[ISP] is implemented by the following pins. SCLK: Serial Clock SDATA: Serial Data
7.1.1.1. WRITE OPERATION Write transaction between the ISP and a host is the similar as the well-known I2C serial interface except that only one byte transfer at each transaction is allowed. The transaction consists of follows. START CONDITION, DEVICE ADDR + R/W[0], SUB ADDR, WRITE DATA, and STOP CONDITION states. The single write access sequence is as
S
DEVICE ADDR
A1
SUB ADDR
A2
WRITE DATA
A3
P
[S] [ DEVICE ADDR ] [ A1 ] [ SUB ADDR ] [ A2 ] [ WRITE DATA ] [ A3 ] [P]
Operation start condition ISP 40h(010_0000 + 0), CIS 22h(001_0001 + 0) device address + R/W bit Acknowledge from ISP ISP Sub address space 80h ~ FFh CIS Sub address space 00h ~ 7Fh Acknowledge from ISP Register Value from host Acknowledge from ISP Operation stop condition
7.1.1.2. READ OPERATION Read transaction between the ISP and a host proceeds as the following sequence. START CONDITION
SUB ADDR START CONDITION DEVICE ADDR + R/W[1] READ DATA STOP CONDITION
DEVICE ADDR + R/W[0] The ISP register access throughput is one byte at each read transaction. But the
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CMOS Image Sensor register access through the ISP chip needs two sequential read operations to compensate the read access delay from CMOS Image Sensor to ISP. The second read data for the CMOS image sensor register should be recognized as the right value of the accessed register. But when the ISP auto functions are enabled, there will be a variable delay for the right data transfer from the CMOS image sensor to the ISP at the first read access, so the second read access may not get acknowledge from the ISP until the first read access is completely processed in the ISP. To take care of the said situation, a system host should repeat the second read access until it get acknowledge from the ISP or there should be sufficient delay between two accesses. To summarize, the ISP general register read access is always completed by only one read transaction, and the CMOS image sensor register access needs two fully acknowledged read transactions and the last read data is the right value for the accessed register. The single read access sequence is as follows.
S1
DADDR 1
A1
SADDR
A2
S2
DADDR 2
A3
READ DATA
A4
P
[ S1 ] [ DADDR 1 ]
Start condition Device Address ISP 40h(010_0000 + 0), CIS 22h(001_0001 + 0) device address + R/W bit
[ A1 ] [ SADDR ] [ A2 ] [ S2 ] [ DADDR 2 ]
Acknowledge from ISP ISP Sub address space 80h ~ FFh CIS Sub address space 00h ~ 7Fh Acknowledge from ISP Start condition Device Address ISP 41h(010_0000 + 1), CIS 23h(001_0001 + 1) device address + R/W bit
[ A3 ] [ READ DATA ] [ A4 ] [P]
Acknowledge from ISP Register Value from ISP Acknowledge from HOST Stop condition
* Note ( Importance ! ) ISP General Register Read : 1 Read Operation needed. CIS Register Read : 2 Read Operation needed, valid data at second read operation. ISP recognize CIS read command at first read.
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7.1.1.3. Data Transfer Timing on the serial Interface
SDA
SCL
1-7 1-7
S START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK
8
9
1-7
8
9
1-7
8
9
P STOP CONDITION
7.1.2. Host Parallel Interface H1A424M167 ISP supports an external 8-bit microcontroller interface to access H1A424M167 internal registers. Basically, the data transfer operations(8bits) are multiplexed on the address bus.
CSB ALE IOR IODone
Stretched
AD[7:0]
A[7:0]
D[7:0]
Valid D[7:0]
Host Parallel Read Operation
A Parallel read operation always needs only 1 read cycle different from the serial read operation. But the host must watch `IODone' signal for a proper read operation. IODone signal indicates the completion of read/write operation. So the host must hold the IOR, CSB signals until IODone signal is active, to read the valid data on AD[7:0] lines. At the final stage, the host ends the bus cycle(CSB, IOR) then IODone signal become inactive.
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CSB ALE IOW IODone
Stretched
AD[7:0]
A[7:0]
D[7:0]
Stretched
Active write operation
Host Parallel Write Operation
Similar to parallel read operation, parallel write operation needs only 1 operation cycle. The host must watch `IODone' signal for a proper write operation. IODone signal indicates the completion of read/write operation. So the host must hold the IOW, CSB, Write Data[7:0] signals until IODone signal become active. When IODone signal become active, ISP accept the write data internally. At the final stage, the host ends the bus cycle(CSB, IOW, Write Data[7:0]) and IODone signal become inactive. ISP holds IODone active until read/write operation is completed. CIS register read/write operation needs more time than ISP register read/write operation. So IODone active signal for CIS register read/write operation is much longer than that of ISP register read/write operation. 7.1.3. Serial or Parallel Interface selection The selection between serial interface and parallel interface is made at hardware reset time. If CSB/MODE pin, pin number 64, is pulled down during reset, Serial Interface is configured, and otherwise parallel interface is selected. For example, Serial Interface selection timing is as below.
RESETB
Serial Interface Selection
More than 64 MCLK
CSB/MODE
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7.2. Clock(MCLK, PCLK, VCLK) Timing Diagram
This chart shows the timing diagram in the YCbCr 4:2:2, 16bit video mode.
MCLK
PCLK
VCLK
Y[7:0]
Y0 U0
Y1 V0
Y2 U2
Y3 V2
Y4 U4
Y5 V4
UV[7:0]
OP_MODE (VGA) VCLK
Y[7:0]
Y0 U0
Y1 V0 OP_MODE (SIF,CIF,QSIF,QCIF)
Y2
UV[7:0]
U2
* Note : HV7131B(VGA) CMOS Sensor is used for this timing diagram.
7.3. Video Output Interface
The H1A424M167 outputs video data in YUV 4:2:2 format through the 16-bit (Y[7:0] and UV[7:0]) data bus. Video data is changed at the rising edge of the VCLK signal. UV order can be selected by programming OUT_FORM register. VCLK frequency is same to PCLK frequency in VGA mode when the 16-bit video mode is enabled. VCLK frequency is a half of PCLK frequency in SIF,CIF,QSIF,QCIF modes when the 16-bit video mode is enabled. (See OP_MODE register description.) Some video codec needs several HSYNC pulses within active VSYNC. So, The H1A424M167 can modify input VSYNC width by programming HSYNC_COUNT register for VSISP pulse to contain several HSYNC pulses. All YUV 16bit ports are active for every HSISP lines in YUV 4:2:2, 16bit video mode. All YUV 16bit ports are active for even HSISP lines, and only Y 8bit ports are active for
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odd HSYNC lines in YUV 4:2:0, 16bit video mode. The following chart shows the video output data format in the 4:2:2, 4:2:0,16bit video mode.
VSISP HSISP Y[0..8] UV[0..8]
Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3
U0 V0 U2 V2
U0 V0 U2 V2
U0 V0 U2 V2
U0 V0 U2 V2
YCbCr 4:2:2, 16bit format, Cb first
VSISP HSISP Y[0..8] UV[0..8]
Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3 Y0 Y1 Y2 Y3
Don't Care
U0 V0 U2 V2
Don't Care
U0 V0 U2 V2
YCbCr 4:2:0, 16bit format, Cb first
VICLK
Y[7:0]
Y0 U0
Y1 V0
Y2 U2
Y3 V2
Y4 U4
Y5 V4
UV[7:0]
OUT_FORM (Cr first) Y[7:0] Y0 V0 Y1 U0 Y2 V2 Y3 U2 Y4 V4 Y5 U4
UV[7:0]
OUT_FORM (Cb first)
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7.4. Relations between input video timing and output video timing
The H1A424M167 have five modes of video output timing - VGA(640X480), CIF(352X288), SIF(320X240), QCIF(176X144), QSIF(160X120) - , when the CMOS Image sensor operates in mode of VGA(640X480). The first pixel color of a frame should be "RED" in order to get correct color interpolated image. The following timing diagrams show relations on each mode. 7.4.1. VGA
VSYNC HSYNC SENSOR DATA
Output Delay not considered.
CIS Output Timing
VSISP HSISP YUV ISP Output Timing
7.4.2. CIF
VSYNC HSYNC SENSOR DATA
Output Delay not considered.
CIS Output Timing
VSISP HSISP
YUV ISP Output Timing
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7.4.3. SIF
VSYNC HSYNC SENSOR DATA
Output Delay not considered.
CIS Output Timing
VSISP HSISP
YUV ISP Output Timing
7.4.4. QCIF
VSYNC HSYNC SENSOR DATA
Output Delay not considered.
CIS Output Timing
VSISP HSISP
YUV ISP Output Timing
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7.4.5. QSIF
VSYNC HSYNC SENSOR DATA
Output Delay not considered.
CIS Output Timing
VSISP HSISP
YUV ISP Output Timing
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8. Register Description
8.1. Registers Mnemonic Table
l BASE Registers Table Register Name Operating Mode Register Base Function Enable Register Scale Width Control Upper Register Scale Width Control Lower Register CMA11 Register CMA12 Register CMA13 Register CMA21 Register CMA22 Register CMA23 Register CMA31 Register CMA32 Register CMA33 Register OFSR Register OFSG Register OFSB Register l AUTO Registers Table Register Name Auto Function Enable Register AWB/AE Window Horizontal Start Position Ha Horizontal Side Segment Width Hb Horizontal Center Segment Width Hc AWB/AE Window Vertical Start Position Va Vertical Side Segment Height Vb Vertical Center Segment Height Vc Analog Gain-Top Limit Register Analog Gain-Bottom Limit Register WIN_V_SIDE WIN_V_CENTER GAIN_TOP GAIN_BOTTOM A5h A6h A7h A8h 50h 0Ah 3Fh 14h WIN_H_SIDE WIN_H_CENTER WIN_V_START A2h A3h A4h 96h FAh 0Ah Mnemonic AUTO_ENB WIN_H_START Address A0h A1h Default 00h 2Dh Mnemonic OP_MODE BASE_ENB SCALE_UPPER SCALE_LOWER CMA11 CMA12 CMA13 CMA21 CMA22 CMA23 CMA31 CMA32 CMA33 OFSR OFSG OFSB Address 80h 81h 82h 83h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h Default 02h 01h 01h 40h 5Ah F3h F3h F3h 5Ah F3h F3h F3h 5Ah 00h 00h 00h
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AWB Function Control Register AWB Lock Control Register AE Function Control Register AE Lock Control Register Y-target Value Register Reset Level Control Register Exposure Time Limitation Value Upper Byte Exposure Time Limitation Value Middle Byte Exposure Time Limitation Value Lower Byte AWB Cr-target Value Register AWB Cb-target Value Register Anti Flicker Unit Time Upper Byte Anti Flicker Unit Time Middle Byte Anti Flicker Unit Time Lower Byte Lock Status Flags Register(Read Only) l OUT Registers Table Register Name Edge Control Register Output Format Control Register HSYNC Counter Register Manual Histogram Mode Control Register Fixed Contrast Stretching Factor Register Gamma Start 0 Register Gamma Start 1 Register Gamma Start 2 Register Gamma Start 3 Register Gamma Start 4 Register Gamma Start 5 Register Gamma Start 6 Register Gamma Start 7 Register Gamma Start 8 Register
AWB_CONTROL AWB_LOCK AE_CONTROL AE_LOCK Y_TARGET RESET_LEVEL EXP_LMT_UPPER EXP_LMT_MIDDLE EXP_LMT_LOWER AWB_CR_TARGET AWB_CB_TARGET AF_UT_UPPER AF_UT_MIDDLE AF_UT_LOWER STATUS_FLAGS
A9h AAh ABh ACh ADh AEh B0h B1h B2h B3h B4h B5h B6h B7h B8h
76h B5h 55h B5h 80h 20h 14h 58h 55h 80h 80h 01h B2h 07h XXh
Mnemonic EDGE_CONTROL OUT_FORM HSYNC_COUNT HISTO_MODE FIXED_FACTOR GMA_START0 GMA_START1 GMA_START2 GMA_START3 GMA_START4 GMA_START5 GMA_START6 GMA_START7 GMA_START8
Address C0h C1h C2h C3h C4h E0h E1h E2h E3h E4h E5h E6h E7h E8h
Default 0Dh 08h 06h 00h 00h 20h 2Dh 37h 47h 5Fh 72h 83h B6h DEh
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Gamma Slope 0 Register Gamma Slope 1 Register Gamma Slope 2 Register Gamma Slope 3 Register Gamma Slope 4 Register Gamma Slope 5 Register Gamma Slope 6 Register Gamma Slope 7 Register Gamma Slope 8 Register
GMA_SLOPE0 GMA_SLOPE1 GMA_SLOPE2 GMA_SLOPE3 GMA_SLOPE4 GMA_SLOPE5 GMA_SLOPE6 GMA_SLOPE7 GMA_SLOPE8
E9h EAh EBh ECh EDh EEh EFh F0h F1h
19h 28h 1Fh 18h 13h 10h 0Ch 09h 08h
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8.2.
BASE Register Map ( MCU Address Space 80h~95h )
8.2.1. Normal Register[80h~83h]
Operating Mode Register[80h]
[7] [ 7..6 ] [6] [5] [4] [2] [1] Sensor PCLK divider 0 : MCLK/3, 1: MCLK/6, 2: MCLK/12, 3: MCLK/24 * Note : Normally, use MCLK/3 with VGA(HV7131X), CIF(HV7121X) CIS [ 5..4 ]
[02h]
[0] [R/W]
ISP Clock divider [R/W] 0 : MCLK/3, 1: MCLK/6, 2: MCLK/12, 3: MCLK/24 * Note : Normally, use MCLK/3 with VGA(HV7131X) CIS, MCLK/6 with CIF(HV7121X) CIS [ 2..0 ] Operating Mode Set [R/W] 1 0 0 : VGA ( 1 to 1 Mode ) 0 1 1 : C I F ( Subsample Mode ) 0 1 0 : S I F ( Subsample Mode ) 0 0 1 : QCIF ( Subsample Mode ) 0 0 0 : QSIF ( Subsample Mode ) These bits specifies which one of color interpolation methods is used, VGA : color interpolation using 3x3 spatial kernel CIF/SIF : color interpolation using 3/4 subsampling using 2x2 kernel QCIF/QSIF : color interpolation using 3/16 subsampling using 4x4 kernel and also specifies which one of input image size scalings is used. VGA : 1/1 scaling CIF/SIF : 1/4 scaling QCIF/QSIF : 1/16 scaling a) Subsampling mode definitions 3/4 subsampling : 2x2 Bayer Data for four sensor pixels. R/G/B Data for a output pixel in CIF/SIF mode. Subsampling window moves by 2 pixels in horizontal and vertical directions. 3/16 subsampling: 4x4 Bayer Data for sixteen sensor pixels. R/G/B Data for a output pixel in QCIF/QSIF mode. Subsampling window moves by 4 pixels in horizontal and vertical directions. b) In VGA(1 to 1 Mode) mode operation, ISP needs the input image with 642 X 482 size for horizontal and vertical interpolation. In CIF,SIF,QCIF,QSIF (Subsample Mode) mode operation, ISP needs the input image with 640 X 482 for vertical interpolation. The reason that vertical height is two lines plus 480 is that internal ISP logic requires two lines timing margin to support CIF/QCIF/X-flip functions. For CIF mode, horizontal blank period of a sensor must be larger than 64 pixel clock.
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Base Function Enable Register[81h]
[5]
[01h]
[4]
[3]
[2]
[1]
[5] [4] [3] [2] [1] [0] RB Interpolation Mode Set [R/W] Two R/B color interpolation methods are supported when R or B color component is interpolated from neighbor pixels's information for full RGB color in VGA mode: a) average mode that interpolates missing R or B by just averaging neighbor R or B pixels, b) chromacity mode that interpolates missing R or B from utilizing neighbor chromacitis values, (R-G) or (B-G). This bit specifies which one of the color interpolation methods is used 1 : Average, 0 : Chromacity G Interpolation Mode Set [R/W] Two G color interpolation methods are supported when G color component is interpolated from neighbor G pixels's information for full RGB color in VGA mode: a) median mode that interpolates missing G by averaging median neighbor G values excluding maximum/minimum neighbor G values. b) average mode that interpolates missing G by averaging all neighbor G values. This bit specifies which one of G color interpolation methods is used 1 : Median, 0 : Average X-Flip Function Enable [R/W] The function enables the horizontal flip(left-right changed) of input image data. In oder to get the flipped standard image size(640x480) with VGA interpolation mode selected, input image data input size should be 642x483 that height size is one more line increased, to account for Bayer input data to be flipped before any processing proceeds. For other flipped image size format outputs(CIF/SIF/QCIF/QSIG), the input image size is the same as that for unflipped image data out, 640x482. 1: X-Flip ON, 0 : X-Flip OFF Gamma Function Enable [R/W] Piecewise linear gamma approximation method is implemented. Precise piece linear segments are supported and user-programmable. For more details, refer to gamma register description section. 1 : Gamma ON, 0 : Gamma OFF Color Matrix Function Enable [R/W] This function compensates color spread effect of color filters and sensing circuits to get the optimal pure color reproduction. color matrix coefficients are programmable from -127/64 to 127/64. Offset compensation registers are also supported. 1 : Color Matrix ON, 0 : Color Matrix OFF
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[0]
Color Interpolation Function Enable [R/W] This bit specifies whether color interpolation is processed or not. Color interpolation methods are defined by OP_MODE register. Most importantly, in order to have a correct color interpolation, the first input pixel data type should be R pixel data. 1 : Interpolation ON, 0 : Interpolation OFF
* Note : The start pixel of every input frame must be R for proper interpolation.
Scale Width Control Upper Register[82h]
[0] Scale Width Control Upper Value
[01h]
[0] [R/W]
Scale Width Control Lower Register[83h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Scale Width Control Lower Value
[40h]
[0] [R/W]
* Note : The scale width control register is only related to operating mode CIF/SIF/QCIF/QSIF, and controls how many column data in each line are output. Default value is 140h(340d), the half of standard VGA width size.
8.2.2. Color Matrix Coefficients Value[8Ah ~ 95h] These registers are used in color matrix function in order to compensates color spread effect of color filters and sensing circuits to get the optimal pure color reproduction. Color matrix coefficients are programmable from -127/64 to 127/64. Programming register value for intended color matrix coefficients should be resolved by the following sequence. For positive values, CMAxx = Integer(RealCoefficientValue x 64); For negative values, CMAxx = TwosComplement(Integer(RealCoefficientValue x 64)); RealCoefficientValue values from -127/64 to 127/64 can be programmed. Offset compensation registers are also supported.
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l Fundamental color matrix equation CMA11 CMA12 CMA13 R OFSR CMA21 CMA22 CMA23 G + OFSG CMA31 CMA32 CMA33 B OFSB
CMA11 Register[8Ah]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA11 Value X 64
[5Ah]
[0] [R/W]
CMA12 Register[8Bh]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA12 Value X 64
[F3h]
[0] [R/W]
CMA13 Register[8Ch]
[7] [ 7..0 ] [7] [ 7..0 ] [6] [5] [4] 2's Complement [4] 2's Complement [3] [2] [1] [3] [2] [1] CMA13 Value X 64 [6] [5]
[F3h]
[0] [R/W]
CMA21 Register[8Dh]
CMA21 Value X 64
[F3h]
[0] [R/W]
CMA22 Register[8Eh]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA22 Value X 64
[5Ah]
[0] [R/W]
CMA23 Register[8Fh]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA23 Value X 64
[F3h]
[0] [R/W]
CMA31 Register[90h]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA31 Value X 64
[F3h]
[0] [R/W]
CMA32 Register[91h]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA32 Value X 64
[F3h]
[0] [R/W]
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CMA33 Register[92h]
[7] [ 7..0 ] [6] [5] [4] 2's Complement [3] [2] [1] CMA33 Value X 64
[5Ah]
[0] [R/W]
OFSR Register[93h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Color Matrix Red Offset Value -127 ~ +128 2's complement
[00h]
[0] [R/W]
OFSG Register[94h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Color Matrix Green Offset Value -127 ~ +128 2's complement
[00h]
[0] [R/W]
OFSB Register[95h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Color Matrix Blue Offset Value -127 ~ +128 2's complement
[00h]
[0] [R/W]
* Note : The values of CMA11~CMA33 are allowed between -2 and 2
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8.3. AUTO Register Map ( MCU Address Space A0h ~ B4h )
8.3.1. Function Enable Register[A0h]
Auto Function Enable Register[A0h]
[7] [7] [6] [5] [6] 1 : ENB enable, AE Mode Control 1 Used with AE mode control 0 at bit 0 Auto Histogram Equalization Enable [5] [4] [3] [1] Image Sensor ENB Control 0 : ENB disable
[00h]
[0] [R/W] [R/W] [R/W]
Automatically enables the histogram equalization function when larger exposure time than exposure time limit value defined at the registers B0 ~ B2 is needed to achieve Y target brightness. This bit is not valid when manual histogram equalization defined at register C3h is enabled. 1 : Auto Histogram Equalization ON 0 : Auto Histogram Equalization OFF [4] Automatic Reset Level Control [R/W] Automatically controls the Reset Level of CMOS Image Sensor. Low Reference Count Register and High Reference Count Register (Hyundai CMOS Image Sensor Registers, Addressed 57h 58h 59h 5ah) denote the current sampling condition. when the ARC function enable, ARC logic reads these register values and compares with the threshold value within the Reset Level Control Register(ISP Register Addressed AEh). If the low reference count or high reference count is larger than the value of Reset Level Control Register, ARC Logic considers Reset Level is not suitable for fine sampling, and update the appropriate Reset Level Value in the Reset Level Register(30h) of HYUNDAI CMOS Image Sensor. 1 : ARC on, [3] 0 : ARC off [R/W] Automatic G-color gain Control
AWB Logic control only the R, B color gain of CIS. So, for getting better color balance and using large analog gain range, G color gain must be controlled. If this function(AGC) is enabled, AGC Logic control appropriate G-color gain level automatically. It may be disabled, when the analog gain range(Limited by analog gain Top, Bottom Limit Register) is too small. 1 : AGC on, 0 : AGC off
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[1] [0]
AWB Function Control 1 : AWB On, AE Mode Control 0 Define AE mode with AE mode control 1 at bit 6 AE mode control 1 0 0 1 AE mode control 0 0 1 X AE mode AE disable AE pixel mode 0 : AWB Off
[R/W] [R/W]
AE anti-flicker mode
8.3.2. AWB/AE Windows Configuration Registers[A1h~A6h] Hyundai H1A424M167 analyze the input image from the CMOS Image Sensor, base on the 9 programmable windows for AE and AWB. The AE and AWB function use Y and U,V values from 9 independent windows to adjust brightness and to correct color balance. l AWB/AE Windows Configuration Full Frame Window
Ha Hb Hc Hb
AE Window
Va Vb Vc Vb A
Window
B
Window
A
Window
B
Window
C
Window
B
Window
A
Window
B
Window
A
Window
AHstartAReg(Ha) AHstartBReg(Hb) AHstartCReg(Hc) AVstartAReg(Va) AVstartBReg(Vb) AVstartCReg(Vc)
AWB/AE Window Horizontal Start Position Ha [A1h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] A-Windows Horizontal Size Pixel Count Value
[2Dh]
[0] [R/W]
Horizontal Side Segment Width Hb [A2h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] B-Windows Horizontal Size Pixel Count Value
[96h]
[0] [R/W]
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Horizontal Center Segment Width Hc [A3h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] C-Windows Horizontal Size Pixel Count Value
[FAh]
[0] [R/W]
AWE/AE Window Vertical Start Position Va [A4h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] A-Windows Vertical Size Pixel Count Value
[0Ah]
[0] [R/W]
Vertical Side Segment Height Vb [A5h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] B-Windows Vertical Size Pixel Count Value
[50h]
[0] [R/W]
Vertical Center Segment Height Vc [A6h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] C-Windows Vertical Size Pixel Count Value
[0Ah]
[0] [R/W]
* Note : When the display mode is not VGA, Horizontal Configuration value (Ha, Hb, Hc) have to be programmed as two times larger value of actual Horizontal display size. 8.3.3. Normal Register[A7h~B8h]
Analog Gain-Top Limit Register[A7h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Analog Gain-Top Value(Analog Gain Level Boundary)
[3Fh]
[0] [R/W]
Analog Gain-Bottom Limit Register[A8h]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] Analog Gain-Bottom Value(Analog Gain Level Boundary)
[14h]
[0] [R/W]
CMOS Image Sensor supports analog gain function to amplify the pixel analog output of CMOS Sensor. Available programmable range is 0 - 63. If the analog gain is too large or too small, the dynamic range of sensor pixel output is not suitable for fine scene. These registers(A7h,A8h) define the usable analog gain range (maximum and minimum gain) of CIS for ISP to control R,G,B gain of CMOS Image Sensor within this range. Available programmable range is 0 - 63 and the value of analog gain-Top limit register must be larger than the value of analog gain-Bottom Limit register.
AWB Function Control Register[A9h]
[7] [6] [5] [4] [3] [2] [1]
[76h]
[0]
This Register is used to define the pixels to be accumulated for AWB. Only the pixels
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within the defined color and luminous range on this register will be used for AWB. [ 7. .5 ] Cr+Cb Range Selector [ 4. .2 ] Cr Range Selector * Note : 0 to 7 are allowed for Cr+Cb range and Cr range. Larger value means wider AWB white spot. [1] Luminous Range selector 1 : Reject too Dark and too Bright pixels for AWB 0 : Use all pixels for AWB [0] AwbWin 0 : Whole 9 AWB windows used 1 : Only center AWB window used [R/W] [R/W]
[R/W]
[R/W]
AWB Lock Control Register[AAh]
[7] [6] [5] [4] [3] [2] [1]
[B5h]
[0]
This Register is used for AWB Lock Control. The difference between Cr/Cb target and current frame Cr/Cb mean is used for AWB lock/unlock scheme. As the difference is smaller, we can get the good white balanced image. The difference is compared with AWB lock range value and AWB unlock range value. If current state is out of white balance, AWB logic change the R/B gains of CMOS Image Sensor to make the difference less than the lock range value. If the difference is less than lock range value, we consider white balance is achieved and no more gain control made. After getting white balanced image we have to compare the difference with unlock range value to check the image is out of white balance or not. If the difference is larger than the unlock range value, AWB logic start to change R/B gains again to find new white balance point. [7] AWB Lock_Unlock Function Enable Bit both Locking and unlocking. AWB lock range is not used. 1 : Lock, Unlock Function Enable. In this case AWB lock range and AWB [ 6..4 ] [ 3..0 ] unlock range are defined separately for locking and unlocking. AWB Lock Range AWB Unlock Range [R/W]
0 : Lock, Unlock Function Disable. In this case AWB Unlock Range is used for
* Note : When AWB lock_unlock function is enabled, AWB unlock range have to be larger than the lock range. As the larger value of lock/unlock range, we can get the stable image. And as the small value of lock/unlock range, we can get the fine white balanced image.
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l
Windows Defined for AE a b a b c b a b a
AE Function Control Register[ABh]
[7] [ 7..6 ] [6] Weight Mode [5] [4] [3] [2] [1]
[55h]
[0] [R/W]
These Bits are used to select weight mode of AE Function. When block weight mode is selected, nine AE windows have different weight. When window weight mode is selected, nine AE windows have same weight and all the pixels in the center window(window-c) and window-b will be used for AE but pixels in the window-a are limited by bit 4 Wweight. When block and window mixed mode, AE windows have different weights and pixel limit function is on too by bit 4 Wweight. When Weightless mode is selected, all the original pixel value in the nine AE windows will be used for AE. 00 : Bweight(Block weight) Mode only. 01 : Wweight(Window weight) Mode only. 10 : BWeight + Wweight 11 : Weightless Mode Bweight Two kinds of Block Weight are available when Block weight mode. 0 : Smaller center window weight ( a < b < c ) 1 : Larger center window weight ( a < b << c ) Wweight Windows Weight Selector for AE when Wweight Mode Valid. 0 : Larger Y range is used. 1 : Smaller Y range is used. Anti_Flicker_Control (Lock Range Selector) unstable , large value means rough AE control but stable. Histogram Equalization Fine Control Equalization function is on(Auto Function enable Register[5] = 1). 0 : Use small contrast stretching value 1 : Use large contrast stretching value Exposure Time update rate control. This bit is used to set the exposure time update rate.
[5]
[R/W]
[4]
[R/W]
[ 3..2 ]
[R/W]
Lock range select for Anti-flicker mode. Small value means fine AE control but [1] [R/W]
This bit defines the Histogram Equalization method when the Histogram
[0]
[R/W]
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0 : Every 2-frame. 1 : Every 3-frame.
AE Lock Control Register[ACh]
[7] [6] [5] [4] [3] [2] [1]
[B5h]
[0]
This Register is used for AE Lock Control. The difference between Y target and current frame Y mean is used for AE lock/unlock scheme. As the difference is smaller, we can get the close brightness we want . The difference is compared with AE lock range value and AE unlock range value. If current state is out of target brightness, AE logic change the integration time of CIS to make the difference less than the lock range value. If the difference is less than lock range value, we consider exposure target is achieved and no more integration time control made. After getting target brightness we have to compare the difference with unlock range value to check the image is out of target brightness or not. If the difference is larger than the unlock range value, we have to change integration time again to adjust frame brightness. This register is valid only when AE pixel mode is enabled. [7] AE Lock_Function Enable Bit all locking and unlocking. AE lock range is not used. 1 : Lock, Unlock Function Enable. In this case, AE lock range and AE unlock [ 6..4 ] [ 3..0 ] range are used for locking and unlocking each. AE Lock Range AE Unlock Range [R/W]
0 : Lock, Unlock Function Disable . In this case, AE Unlock Range is used for
Y-target Value Register[ADh]
[7] [ 7..0 ] [6] [5] [4] [3] [2] [1] AE Target Luminous Value Register.
[80h]
[0] [R/W]
Reset Level Control Register[AEh]
[7] [6] [5] [4] [3] [2] [1] [ 7..0 ] Threshold Pixel Count Value of the Invalid Reference Value.
[20h]
[0] [R/W]
This Register is used to set the maximum Invalid Pixel Count, produced from CIS sampling(data Read). So, as the small value of this Register, we can get the fine scene. This register valid only when ARC Function(A0h[4]) is enabled.
Exposure Time Limitation Value Upper Byte[B0h]
[7] [6] [5] [4] [3] [2] [1]
[14h]
[0]
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Exposure Time Limitation Value Middle Byte[B1h]
[7] [6] [5] [4] [3] [2] [1]
[58h]
[0]
Exposure Time Limitation Value Lower Byte[B2h]
[7] [6] [5] [4] [3] [2] [1]
[55h]
[0]
These three Exposure Time Limitation Value Registers(24Bits) are used to set the minimum Frame-Rate. It defines maximum exposure time that can be programmed to CIS integration time registers. And, It must be programmed as multiple of Anti Flicker Unit Time Register(24Bits) when AE anti_Flicker mode is enabled.
AWB Cr-target Value Register[B3h]
[7] [6] [5] [4] [3] [2] [1]
[80h]
[0]
AWB Cb-target Value Register[B4h]
[7] [6] [5] [4] [3] [2] [1]
[80h]
[0]
These Cr, Cb-target Registers are used for controlling Frame Color. AWB logic use these values for a white balance matching. To make a frame reddish, Increase the Cr target register value over 80h or decrease the Cb target register value under 80h.
Anti Flicker Unit Time Upper Byte[B5h]
[7] [6] [5] [4] [3] [2] [1]
[01h]
[0]
Anti Flicker Unit Time Middle Byte[B6h]
[7] [6] [5] [4] [3] [2] [1]
[B2h]
[0]
Anti Flicker Unit Time Lower Byte[B7h]
[7] [6] [5] [4] [3] [2] [1]
[07h]
[0]
Anti Flicker Unit Time Registers(24Bits) should be used to define the time step of changing integration time register. AE Anti-Flicker mode is used to remove horizontal banding noise under fluorescent lamp. When AE anti-flicker mode is enabled, the integration registers of a CIS are programmed as multiple of this unit time. These registers are valid only when AE anti-flicker mode is enabled. When AE pixel mode is enabled, Anti flicker Unit time Registers(24Bits) are used to set exposure time bottom limitation.
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Lock status Flags Register[B8h]
[2] [1]
[R-O]
[0]
User can read the current AE/AWB status using this register. This register can be used to choose a fine image for digital still camera application. [2] Automatic Stretching Status Flag [Read Only] 0 : Automatic Stretching is Disable. [1] 1 : Automatic Stretching is Enable. AWB Lock Status Flag 0 : Current AWB status is Unlock. 1 : Current AWB status is Lock. AE Lock Status Flag 0 : Current AE status is Unlock. 1 : Current AE status is Lock. [Read Only]
[0]
[Read Only]
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8.4. OUT Register Map ( MCU Address Space C0h ~ F1h )
8.4.1. Normal Register[C0h~C2h]
Edge Control Register[C0h]
[3] [3] [2] [1] 1 : Edge Function Enable, 1 : Use Edge Transfer Function, Edge detection filter select 1: 0: -1/2, 0, 0, -1/2, 1, 1, 0, 0, -1/2 -1/2 [2] [1] 0 : Edge Function Disable
[0Dh]
[R/W] [R/W]
0 : Bypass Edge Transfer Function[R/W]
Output Format Control Register[C1h]
[5] [5] [4] [3] [2] [1] 0 : Use CCIR-601 Color Space Conversion equation 1 : Use JFIF Color Space Conversion equation * Note : Color Space Conversion Equation l CCIR 601 Range: 16 ~ 235 Range: 16 ~ 240 Range: 16 ~ 240
[08h]
[0] [R/W]
Y=
77R + 150G + 29B 256 - 44R - 87G + 131B Cb = + 128 256 131R - 110G - 21B Cr = + 128 256
Reverse CCIR 601
l
R = Y + 1. 336 ( Cr - 128 )- 0 .002 ( Cb - 128 ) G = Y - 0 .700 ( Cr - 128 )- 0 . 334 ( Cb - 128 ) B = Y - 0 .006 ( Cr - 128 )+ 1.732 ( Cb - 128 )
l CCIR 601-256 [JFIF]
Y=
77R + 150G + 29B 256 - 43R - 85G + 128B Cb = + 128 256 128R - 107G - 21B Cr = + 128 256
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l
Reverse CCIR 601-256[JFIF]
R = Y + 1. 402 ( Cr - 128 ) G = Y - 0 . 34414 ( Cb - 128 )- 0 .71414 ( Cr - 128 ) B = Y + 1.772 ( Cb - 128 )
[ 4..3 ] 10 : YUV 4:2:2 11 : YUV 4:2:0 00, 01 : Don't Care [2] [1] [0] 0 : 16bits YCrCb when 4 : 2 : 2 or 4 : 2 : 0 1 : 8bits YCrCb when 4 : 2 : 2 or 4 : 2 : 0 0 : Y first when 8bits YCrCb 1 : CrCb first when 8bits YCrCb 0 : Cr first when YCrCb 4 : 2 : 2 or 4 : 2 : 0 1 : Cb first when YCrCb 4 : 2 : 2 or 4 : 2 : 0 * Note : 8bits output format function cannot be guaranteed.(under testing) [R/W] [R/W] [R/W] [R/W]
HSYNC Counter Register [C2h]
[4] [3] [2] [1]
[06h]
[0]
This Register should be used to program the HSYNC Count during Vertical retrace Time. This register defines number of lines for VSYNC pulse to be extended. Some video signal processing chips like Winbond W9967, need VSYNC period as multiple of line period. To support these chips with HYUNDAI CMOS Image Sensor, this register have to have non-zero value. [ 4..0 ] HSYNC Counter Value ( 0 ~ 31 ) [R/W]
8.4.2. Histogram Equalization Control Register[C3h~C4h]
Manual Histogram Mode Control Register[C3h]
[3] [3] Manual Histogram Function [2] [1]
[00h]
[0] [R/W]
1 : Manual Histogram equalization enable. If enabled, all the Y values of the pixels are stretched with fixed contrast stretching factor defined at register C4. In this case, auto histogram equalization function dose not work. 0 : Manual histogram equalization disable. In this case, histogram function is affected by auto histogram equalization function. [ 2 ..1] Knee point select [R/W]
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Increasing this value move knee point toward 0. Decreasing this value move knee point toward 255. Valid when knee function is enabled. [0] Knee Function Enable. 0 : Disable 1: Enable. [R/W]
Fixed Contrast Stretching Factor Register[C4h]
[7] [6] [5] [4] [3] [2] [1]
[00h]
[0]
This register is used for manual contrast stretching function. Program value should be multiplied stretching Factor by 32(decimal) for the Reducing Rounding Error. Stretching Factor can be 0 ~ 8. 8.4.3. Gamma Control Register[E0h~F1h] Gamma Start0 ~ Start8 Register[E0h~E8h] Gamma Slope0 ~ Slope8 Register[E9h~F1h] Piecewise linear gamma approximation method is implemented. Nine piece linear segments are supported and user-programmable. Gamma Slope Register[E8h] value has effect scaled by 1/8 Gamma Slope Registers[E9h-F1h] value has effect scaled by 1/16
Gamma Start 0 Register[E0h]
[7] [6] [5] [4] [3] [2] [1]
[20h]
[0]
Gamma Start 1 Register[E1h]
[7] [6] [5] [4] [3] [2] [1]
[2Dh]
[0]
Gamma Start 2 Register[E2h]
[7] [6] [5] [4] [3] [2] [1]
[37h]
[0]
Gamma Start 3 Register[E3h]
[7] [6] [5] [4] [3] [2] [1]
[47h]
[0]
Gamma Start 4 Register[E4h]
[7] [6] [5] [4] [3] [2] [1]
[5Fh]
[0]
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Gamma Start 5 Register[E5h]
[7] [6] [5] [4] [3] [2] [1]
[72h]
[0]
Gamma Start 6 Register[E6h]
[7] [6] [5] [4] [3] [2] [1]
[83h]
[0]
Gamma Start 7 Register[E7h]
[7] [6] [5] [4] [3] [2] [1]
[B6h]
[0]
Gamma Start 8 Register[E8h]
[7] [6] [5] [4] [3] [2] [1]
[DEh]
[0]
Gamma Slope 0 Register[E9h]
[6] [5] [4] [3] [2] [1]
[19h]
[0]
Gamma Slope 1 Register[EAh]
[6] [5] [4] [3] [2] [1]
[28h]
[0]
Gamma Slope 2 Register[EBh]
[6] [5] [4] [3] [2] [1]
[1fh]
[0]
Gamma Slope 3 Register[ECh]
[6] [5] [4] [3] [2] [1]
[18h]
[0]
Gamma Slope 4 Register[EDh]
[6] [5] [4] [3] [2] [1]
[13h]
[0]
Gamma Slope 5 Register[EEh]
[6] [5] [4] [3] [2] [1]
[10h]
[0]
Gamma Slope 6 Register[EFh]
[6] [5] [4] [3] [2] [1]
[0Ch]
[0]
Gamma Slope 7 Register[F0h]
[6] [5] [4] [3] [2] [1]
[09h]
[0]
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Gamma Slope 8 Register[F1h]
[6] [5] [4] [3] [2] [1]
[08h]
[0] with
* Note : Gamma Slope Registers Should be Programmed as Multiple of 8 or 16 Others Using 16.
real slope value for reducing rounding error. For the Slope 0 Register, Using 8 and
l
Gamma graph define
Out
Start 8 : : Start 3 Start 2 Slope 1 Start 1 Slope 0 Start 0 0 4 8 16 32 48 64 128 192 255 In
Gamma Control
l Slope register use method
A
Slope
B
A Slope = B
Slope Register Value = Slope x P P = 8 (at Slope 0 Register)
P = 16 (at others Slope Register)
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9. Electrical Characteristics
9.1. Absolute Maximum Ratings
Symbol TAMB TSTG VDD IODD PTOT VI VO Parameter Operating ambient temperature Storage temperature 3.3V DC supply voltage I/O pin voltage with respect to VSS Total power dissipation Input voltage Output voltage Min. 0 -40 3.0 -0.3 -0.3 -0.3 Max 70 125 3.6 VDD + 0.3 182 VDD + 0.3 VDD + 0.3 Unit C C V V mW V V
9.2. DC Characteristics
Symbol IDD MCLK VIL VIH VOL VOH Parameter Supply current Master Clock
Low level input voltage High level input voltage Low level output voltage High level output voltage
Conditions all modes on all modes off -
Min 13.5 2.1Vmin 2.4
Typ 39 36 -
Max 55.2 48 0.8Vmax 0.4 -
Unit mA mA MHz V V V V
* Test condition VDD = 3.3V, Temperature = 25 C; Output load = 10pF; MCLK : 36MHz unless otherwise specified.
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9.3. AC Characteristics
9.3.1. Microcontroller Bus Interface timing (Write cycle)
CSB
Tcs
ALE
Tiop
IOW
IODONE
Tas Tah Tds Twrh
AD[7:0]
A[7:0]
D[7:0]
9.3.2. Microcontroller Bus Interface timing (Read cycle)
CSB
Tcs
ALE
IOR
IODONE
Tas Tah
AD[7:0]
A[7:0]
D[7:0]
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H1A424M167
l Tcs Tas Tah
Microcontroller Bus Timing Description Chip Select setup time Address setup time Address hold time Write data hold time IOW,IOR period time Data setup time Min 0 10 5 5 1 5 Typ Max Units ns ns ns ns
(1)
Time
Twrh Tiop Tds
clk
ns
(1) This is ISP Clock ; Typically, MCLK/3(VGA CIS), MCLK/6(CIF CIS) 9.3.3. Serial Interface Control Timing
stop
start
start
stop
SDATA
Tr Tbuf Tlow Tf Thd;sta
SCLK
Thd;sta Thd;dat Thigh Tsu;dat Tsu;sta Tsu;sto
l Fscl
Serial Interface Timing Description SCL clock frequency Bus free time between a STOP and START condition Hold time START condition LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Rise time of both SDA and SCL signals Min 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb Typ Max 400 0.9 300 Units
KHz
Time Tbuf Thd;sta Tlow Thigh Tsu;sta Thd;dat Tsu;dat Tr
s s s s s s ns ns
1999 October 11
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
Tf Tsu;sto Cb
Fall time of both SDA and SCL signals Setup time for STOP condition Capacitive load for each bus line
20 + 0.1Cb 0.6 -
-
300 400
ns s
pF
9.3.4. RESETB Timing
RESETB
Trst
l Trst
RESETB Timing Description RESETB pulse width LOW Min MCLK * 2 Typ Max Units
Time
9.3.5. Video Output Timing
VICLK
Td
Y[7:0] UV[7:0] HSISP VSISP
l Td
Video Timing Description Video output delay time Min Typ 30 Max 32 Units ns
Time
1999 October 11
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
10. PACKAGE SPEC
1999 October 11
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
11. SOLDERING
11.1. Solder reflow equipment
11.1.1. (Preferred)100% Convection reflow system capable of maintaining the reflow profiles required by EIA/JEDEC standard(JESD22-A113-B). 11.1.2. VPR(Vapor Phase Reflow) chamber capable of operating from 215 C 219 C and/or (2355) C with appropriate fluids. 11.1.3. Infrared(IR)/Convection solder reflow equipment capable of maintaining the reflow profiles required by EIA/JEDEC standard(JESD22-A113-B).
11.2. Reflow Profiles
Convection or IR/Convection Average ramp-up rate(183 C to Peak) Preheat temperature 125(25) C Temperature maintained above 183 C Time within 5 C of actual peak temperature Peak temperature range Ramp-down rate Time 25 C to peak temperature 3 C/second max. 120 second max. 60-150 seconds 10-20 seconds (220+5/-0) C or (235+5/-0) C 6 C/second max. 6 minutes max. 60 seconds 215-219 C or (235+5/-0) C 10 C/second max. VPR 10 C/second max.
11.3. Flux application
After the reflow solder cycles are completed, allow the devices to cool at room ambient for 15 minutes minimum. Apply an activated water soluble flux to the device leads by bulk immersion of the entire parts in flux at room ambient for 10 seconds minimum.
11.4. Cleaning
Clean devices externally using multiple agitated deionized water rinses. No waiting time is required between flux application and cleaning
11.5. Drying
Devices should be dried at room ambient prior to submission to reliability testing.
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